A well known technique for simplifying logic is to arrange a number of a plurality of transistors in a logic tree together to simultaneously process digital signals and provide a single output node. The domino-type of logic circuits utilize this technique by cascading plural NMOS input devices to provide selected logic functions. A PMOS transistor is provided, and is clocked to precharge the output node to a predetermined logic state. Depending on the logic state of the inputs of the input devices, the output node remains at the precharged state, or is pulled low through the series-connected devices by a clocked NMOS device connected to ground. In accordance with the logic NAND function, if all of the NMOS input devices are driven by a logic high level, an output node of the domino circuit will be a logic low. Conversely, if any one of the input NMOS devices is driven with a logic low, the output node of the domino circuit will remain at its precharged logic high state. Because an inversion function is performed with this arrangement, an inverter is generally utilized at the output of the domino circuit to perform an additional logic inversion function so that an overall AND function is realized.
While the domino-type of logic circuit provides a speed advantage, as well as reduced wafer area, this logic family is susceptible to a severe drawback. Because the domino-type of logic is dynamic, i.e., relies on the sustained logic state by charging the parasitic capacitances of the output node, the finite charge precharged at the node must be distributed to each input NMOS device to charge the drain-source capacitance of each such device. When the number of cascaded NMOS input devices becomes large, a number of turned on input devices may cause the output node to become significantly discharged. When this occurs, the output of the inverter can change state, even though not all of the input NMOS devices have been driven into conduction. An erroneous logic output is thereby produced which is contrary to the logic AND function which specifies that a high output is produced when all of the inputs are driven to the same logic high state.
The number of input devices, and thus the number of domino inputs, is thereby limited. This can be appreciated as the voltage drop at the circuit output node increases as more cascaded input NMOS devices are driven into conduction. The problem noted above exists when a number of NMOS devices adjacently connected to the output node are turned on, and one or more others are not. Of course, when all input NMOS devices are driven into conduction, the output node is driven to a logic low which satisfies the AND function.
A multiple-output domino logic, known as MODL, allows single logic trees to produce multiple outputs. Thus, MODL avoids replication of circuitry, where possible, by adding precharge devices and static inverters at intermediate nodes of the logic tree to obtain a desired subfunction.
While precharging an intermediate node of a logic tree may somewhat reduce charge sharing, capacitance is added to the tree resulting in reduced speed. Further, the additional capacitive loading necessitates larger pull-down devices to discharge the capacitance, thereby increasing the size of the device.
From the foregoing, it can be seen that a need exists for an improved multiple output domino logic circuit having reduced capacitive loading. Moreover, a concomitant need exists for an improved domino logic family which is yet even higher in speed, and which may be fabricated in a smaller wafer area.